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Sem several Electronics Syllabus

 Sem several Electronics Syllabus Essay

UNIVERSITY OF MUMBAI SYSTEM OF INSTRUCTIONS AND ANALYSIS (R2007) Plan: B. Elizabeth. (ELECTRONICS ENGINEERING) SEMESTER: VII Sr. No Subjects VLSI Design Filtration Design Electric power Electronics and Drives Number of durations of 1Hour Duration of Theory Theory Paper in Address Practical Conventional paper Hours four 100 2 3 four 100 two 3 4 4 Signifies Term Work Oral Total

1 2 3 5

25 twenty-five 25 25

25 twenty-five 25 twenty-five

150 a hundred and fifty 150 one hundred and fifty

2 two

3 3

100 100

Communication Networks

Elective-II 1 ) Wireless communication 2 . Developments in Biomedical Instrumentation a few. Micro personal computer design four. Digital Graphic Processing Design Project -I

5

some

2

three or more

100

twenty-five

25

150

6

some

20 16

25 15 500

a hundred and fifty

25 one hundred and fifty

50 800

TOTAL TERM: VIII

Number of durations of 1Hour Sr. Not any Subjects Improve VLSI Design Lecture some 4 5 Practical

Life long Theory Theory Paper in Paper Several hours

Marks Term Work Mouth Total

1 2 three or more

2 a couple of 2

3 3 a few

100 90 100

25 25 twenty-five

25 twenty-five 25

a hundred and fifty 150 one hundred and fifty

Robotics and Automation

Inlayed Systems and RealTime Development Elective-III 1 ) Advanced Marketing Technologies installment payments on your DSP Cpus and architectures 3. Nerve organs Networks & Fuzzy Devices 4. Gadgets Product Design Project -II

4

4

2

three or more

100

twenty-five

25

a hundred and fifty

5

TOTAL

16

eight 16

-12

50 500

150

95 200

a hundred and fifty 750

School of Mumbai CLASS: M. E. (Electronics Engineering) Term - VII SUBJECT: VLSI Design Intervals per week (each of 60 min. ) Evaluation Program

Lecture 04 Practical 02 Tutorial Hours Theory Examination 3 Useful examination Oral Examination Term Work Total

Marks 75 25 25 150

Component Objective

Articles To familiarize students with the different aspects with the VLSI discipline and to expose important concepts that have sector value Digital System Style I and II, BEC Evolution of logical difficulty in ICs as a function of time, VLSI design movement, Y-chart rendering, design hierarchy/design abstraction levels in digital circuits, ideas of steadiness, modularity and locality, Semi-custom & full custom gadgets MOS capacitor, energy strap diagrams, group bending, level band ac electricity, threshold volt quality calculation, tolerance adjustment, MOSFET linear and saturated operation(GCA), MOSFET capacitance, channel length modulation. Types of climbing, functional restrictions of your own, short route, narrow channel effects, warm electron effects. Wafer finalizing, mask era, oxidation, epitaxy, ion societe, diffusion, metallization, photolithography, method steps pertaining to NMOS & PMOS products, CMOS inverters, latch-up in CMOS as well as its prevention. Process simulation applying CAD equipment Video of manufacturing process to be shown.

Several hours -

Pre-requisite 1 . Introduction to VLSI

goal

2 . Physics of MOSFET

13

a few. Semiconductor making process

03

4. Design and style rules and layout

a few. MOS Inverters

6. Verilog

Need of design rules, NMOS, PMOS and CMOS design guidelines and layouts. Design of NMOS and CMOS Inverter, NAND and NOR gates. Interlayer contacts, Butting and Left contacts. Adhere diagrams, structure of built-in circuits. Conclusion of Boolean expressions in CMOS. Usage of CAD equipment for layout design and simulation. MOS inverters - resistive load - NMOS load pseudo NMOS (Qualitative) and CMOS inverters (quantitative) -calculation of noise margin, calculation of rise, show up and delay times pertaining to CMOS inverter, transistor dimensions and electric power dissipation, series and seite an seite equivalency rules, equivalent inverter (numericals in noise margin calculations, timing calculations, electrical power dissipation, equivalency expected) Basic concepts, structural gate level, switch level, behavior and RTL building. Arithmetic Brake lines in CMOS VLSI – carry appearance ahead adder, high speed adders, subtractors, decoders, multiplexer and multipliers. Sequential circuits' implementation using verilog (Flip-Flop, signs up and counters, state machines).

10

doze

07

Textual content Books: 1 ) Sung-Mo Kang & Yusuf Leblebici, CMOS Digital...

References: UNIVERSITY OF MUMBAI SCHEME OF INSTRUCTIONS AND EVALUATION (R2007) Programme: B. E. (ELECTRONICS ENGINEERING) SEMESTER: VII

Sr

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